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D flip flop VHDL implementation with buffer, signal and variable compared

- Tuesday, July 7, 2015 No Comments
D flip flop in vhdl language can be implemented by declaring the output Q as buffer, using signal and variable to store the immediate values and later assign them to the output.

Here we show these implementation methods.

Using Buffer we can write D flip flop in the following way.

library ieee;
use ieee.std_logic_1164.all;

entity Dflipflop is
    port( 
    D : in std_logic;
    clk : in std_logic;
    Q : buffer std_logic;
    Qn : out std_logic       
    );
end Dflipflop;

architecture model of Dflipflop is
begin
    process(clk)
    begin
    if rising_edge(clk) then
        Q <= D;
        Qn <= not Q;
    end if;
    end process;   
end model;

The outputs Q of the D flip flop is buffered here. This is because Q being actually output is assigned to Qn inside the if statement. If we declared Q only as output then we could not use the statement Qn <= not Q. Therefore we have declared Q as buffer.

Following shows the waveforms simulated using Aldec VHDL software-


Another way which is better to implement D flip flop in VHDL is to use a signal or variable.

Following is implementation of D flip flop using signal.

library ieee;
use ieee.std_logic_1164.all;

entity Dflipflop is
    port( 
    D : in std_logic;
    clk : in std_logic;
    Q : out std_logic;
    Qn : out std_logic       
    );
end Dflipflop;

architecture model of Dflipflop is   
signal S : std_logic;
begin
    process(clk)
    begin
    if rising_edge(clk) then
        S <= D;
    end if;
    end process;
    Q <= S;
    Qn <= not S;
end model;

In the above code, S is a signal that stores the value of input D at the rising edge of the clock. This is then assigned to outputs Q and Qn. Notice that in this code we did not declare Q as buffer. This is more desirable.

Following is the VHDL software simulation waveform:




Yet another way to write the above code is to use variables. Following is the VHDL code:

library ieee;
use ieee.std_logic_1164.all;

entity Dflipflop is
    port( 
    D : in std_logic;
    clk : in std_logic;
    Q : out std_logic;
    Qn : out std_logic       
    );
end Dflipflop;

architecture model of Dflipflop is   
begin
    process(clk) 
    variable S : std_logic;
    begin
    if rising_edge(clk) then
        S := D;
    end if;
        Q <= S;
    Qn <= not S;
    end process;

end model;

Using variable has the advantage that it's value is immediately updated. Another point to notice is that variable S has be declared inside the process declaration part. Similarly, unlike in case of using signal the assignment of S to Q and Qn must be inside the process.

Here is the VHDL software simulated waveform for this variable used D flip flop code:





C++ program to calculate the coupling and decoupling capacitor values

- No Comments
Below is a voltage divider biasing circuit for which we want to calculate the coupling capacitor and decoupling capacitor values.


In the above circuit, Cc1 and Cc2 are two coupling capacitors one at the input and the other at the output. Cb is the bypass capacitor. We want to calculate these values for given input signal of certain frequency.

You can calculate the value of the resistor using the VDB resistor values calculator. Here is screenshot of this calculator.


We want to amplify a signal of amplitude 1uV and frequency range of 30Hz to 300Hz.

Then we to calculate the coupling capacitor Cc1 value we have to change the above circuit diagram to its ac equivalent as follows-
 The R1, R2 and Zin(base) are in parallel so their equivalent resistance is-

Req1 = R1 || R2 || Zin(base)

The Zin(base) is calculated with the following formula,

Zin(base) = beta * 25mV/Ie

where re = 25mV/Ie is standard formula for ac emitter resistence

Then we can use the formula for calculating the input coupling capacitor value-

Cc1 = 10 / 2* pi * f * Req1

Similarly we can calculate the output coupling capacitor value Cc2 as follows

Cc2 = 10 / 2* pi * f * Req2

where, Req2 is

Req2 = Rc || RL

The last value to be calculated is the bypass capacitor value. The value of this capacitor can be calculated from the equation below

Cb = 10 / 2 * pi * f * Req3

where Req3 is the value of resistor equivalent to parallel resistors R1, R2 and Re as shown below.

That is,

Req3 = R1 || R2 || Re

Thus in this way we can calculate the coupling and bypass capacitor values required for VDB based amplifier circuit.

The C++ program that calculates this is as follows-

#include <iostream>

using namespace std;

int main()
{
    float R1, R2, Rc, Re, RL, Zinb, Req1, Req2, Req3;
    float beta, f;
    float Ie;
    float Cc1, Cc2, Cb;

    cout << "Enter value of R1 in Kohm: ";
    cin >> R1;
    cout << "Enter value of R2 in Kohm: ";
    cin >> R2;
    cout << "Enter value of Rc in Kohm: ";
    cin >> Rc;
    cout << "Enter value of RL in Kohm: ";
    cin >> RL;
    cout << "Enter value of Re in Kohm: ";
    cin >> Re;
    cout << "Enter value of a.c. current gain(beta): ";
    cin >> beta;
    cout << "Enter value of Emitter Current(Ie) in mA: ";
    cin >> Ie;
    cout << "Enter the lowest frequency(f) of input signal in Hz: ";
    cin >> f;

    Zinb = (beta*25/(Ie))/1000;

    Req1 = R1*R2*Zinb/(R1+R2+Zinb);

    Cc1 = (10/(Req1*2*3.14*f))/1000;

    Req2 = Rc*RL/(Rc+RL);

    Cc2 = (10/(Req2*2*3.14*f))/1000;

    Req3 = R1*R2*Re/(R1+R2+Re);

    Cb = (10/(Req3*2*3.14*f))/1000;

    cout << "\nThe input coupling capacitor(Cc1) value in mF is: " << Cc1;

    cout << "\nThe output coupling capacitor(Cc2) value in mF is: " << Cc2;

    cout << "\nThe bypass capacitor(Cb) value in mF is: " << Cb;

    return 0;

}






Voltage Divider Biasing Resistor Values Calculator download free

- Monday, July 6, 2015 No Comments
Here is a calculator that calculates the resistor values required for voltage divider biasing circuit.

Here is how it looks like.


This calculator helps you to calculate the resistor values if you are using voltage Divider Biasing. You have to enter the supply voltage, you input base current, your output collector voltage, arbitary emitter voltage and arbitary resistor value R1 in order to get all the other resistor values.

http://www.filefactory.com/file/4wuxjhn85w21/vdb_calculator.zip

Moore finite state machine VHDL code without enumerated state types

- No Comments
Most finite state machine vhdl are implemented using enumerated data type for the states of state machine. Here is an example of VHDL code of a finite state machine without using enumerated data types for the states. This code describes a moore machine with 3 states A, B and C.

library ieee;
use ieee.std_logic_1164.all;

entity moore_machine is
    port(
    x : in std_logic;
    rst, clk : in std_logic;
    z : out std_logic   
    );
end moore_machine;

architecture model of moore_machine is
signal state : std_logic_vector(1 downto 0);
constant A : std_logic_vector(1 downto 0) := "00";
constant B : std_logic_vector(1 downto 0) := "01";
constant C : std_logic_vector(1 downto 0) := "10";
begin
    Output_Logic : process(state)
    begin
        case state is
            when A => z <= '0';
            when B => z <= '0';
            when C => z <= '1';
            when others => z <= 'X';   
        end case;
    end process;
   
    Next_State : process(clk, rst)
    begin
        if (rst = '1') then
        state <= A;
       
        elsif rising_edge(clk) then
            case state is
                when A =>
                if(x = '1') then state <= B;
                else state <= A;
                end if;
               
                when B =>
                if(x = '1') then state <= C;
                else state <= B;
                end if;
                   
                when C =>
                if(x = '1') then state <= A;
                else state <= C;
                end if;
               
                when others => state <= "XX";
               
            end case;
        end if;
    end process;   
end model;

As can be seen in the above code, the current state of the FSM and the different states of the FSM are implemented inside the declaration section of the architecture. These are state, A, B and C. The current state called state is implemented as signal data type. The states A, B and C are implemented as constant data type.

state being 2 bits, can assume 00, 01, 10 and 11. Because we have arbitrarily chosen 3 states, the state when 00 is A, when 01 it is B and when it is 10 it is C. The state may assume 11 in which case, we have undefined output and undefined state.