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how to implement Subtractor in Verilog and VHDL code

- Friday, November 27, 2015 No Comments
Here we show how to implement Subtractor using Verilog and VHDL. This helps in comparing code and how they are different in these languages. The subtractor acts on 8 bit input.

The VHDL code of the subtractor is below.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity subtractor is
 x, y : in std_logic_vector(7 downto 0);
 diff : out std_logic_vector(7 downto 0)
end subtractor;

architecture model of subtractor is
 diff <= x - y;
end model;

The Verilog code for the same subtractor is below.

module subtractor
 input [7:0] x,y,
 output [7:0] diff

assign diff = x - y;


Adder Verilog and VHDL code comparison

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Verilog and VHDL are two popular hardware description language. Most of the FPGA chips supports these. Here we show how to design an 8 bit adder in VHDL and Verilog.

The following is the VHDL code for 8 bit adder.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity adder is
 x, y : in std_logic_vector(7 downto 0);
 cin : in std_logic;
 sum : out std_logic_vector(7 downto 0);
 cout : out std_logic
end adder;

architecture model of adder is
signal s, x1, y1 : std_logic_vector(8 downto 0);
   x1 <= ('0' & x);
   y1 <= ('0' & y);
   s <= x1 + y1 + cin;
   sum <= s(7 downto 0);
   cout <= s(8);
end model;

The simulated waveform in VHDL software is below.

Next the same adder design in Verilog language is shown below.

module adder
 input [7:0] x,y,
 input cin,
 output [7:0] sum,
 output cout

assign {cout, sum} = x + y + cin;


The simulated waveform this code is below.

For more tutorials see FPGA design tutorials.

Computer Organization and Architecture / download ebook free

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Download The essentials of Computer Organization and Architecture ebook for free from the link below.

This book is written by Linda Null and Julia Lobur. This book is helpful to computer engineering students and those who want to learn how computer are build. It is about how computers CPU, registers, instruction sets and other are designed and developed for higher speed and performance.

The book starts with important history, then explains the different numbering system that was developed during the course of the history. The operation that can be performed on those numbers are then explained. This includes addition and subtraction from which multiplication, division steams. Once the numbers and operation on numbers are explained, the book teaches how to build digital circuits to do the mathematics. Here the boolean logic, logic gates, the digital components- decoder, multiplexers etc are described. The next chapter is on the computer organization. Here a very simple processor architecture MARIE is explained. The simple process of fetch and execution of instruction is described, assembly language is introduced and control system design using hardwired and microprogram are explained. The next chapter is on instruction set, followed by memory then input output organization, compilers, RISC archiecture, parallel processors, instruction-level parallelism, multiprocessors, performance analysis, management issue and finally the network organization and architecture.

The essentials of Computer Organization and Architecture
Fig: The essentials of Computer Organization and Architecture

Download The essentials of Computer Organization and Architecture

FPGA programming: Counter VHDL code

- Thursday, November 26, 2015 No Comments
Counter are basic component of digital system. Here we show how a counter can be designed on FPGA using VHDL language.

A counter is sequential arithmetic circuit with clock and reset signals inputs and n bit output. If the reset signal input is applied then the counter resets to 0. After that, the counter advances through the 2n on the rising edge of the clock. Structurally, a counter is composed of adder and a flip flop or register. The flip flop is reset to 0 when reset signal is applied. After that the output is fed back to the adder where 1 is added to the value from the flip flop or register. The output from the adder is fed into the flip flop or register where the value is stored. This is again fed back to the adder in synchronization with flip flop or register clock input. Thus a counter is a Finite State Machine. This just explained is shown in the following figure.

Such counter can be described using VHDL code as follows.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity counter is
 clk, rst : in std_logic;
 cnt : out std_logic_vector(7 downto 0)
end counter;

architecture model of counter is
 process(clk, rst) 
 variable count : integer;
  if rst = '1' then
   count := 0;
  elsif rising_edge(clk) then
   count := count + 1;
  end if;
  cnt <= std_logic_vector(to_unsigned(count,8));
 end process;
end model;

How to develop Traffic Light Controller VHDL code?

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Traffic Light Controller is a typical example of Finite State Machine. Here we show how to develop VHDL code for a Traffic Light Controller.

We will consider simple traffic light controller that acts according whether there are any cars on each of the road line. 

Shown below is a crossroad with four traffic lights for each of the incoming road.

Such crossroad is an intersection of two roads A and B.

To design the traffic light controller we need to install two sensors for each road A and B. Also we need to install the four traffic lights.

Let the traffic lights be called La and Lb for each roads A and B. Altogether there are 4 lights.

The two sensors for each of the two roads labelled A and B is as shown,

The sensors works in such a way that whenever the detector detects cars on its radar, it turns ON. When there is nothing on the road it stays Off.

Each of the traffic lights receives digital signal whether it should be green, yellow or red.

Thus the Traffic Light Controller FSM has two inputs Sa and Sb and two outputs La and Lb. We also have to provided some clock signal to make the system work on timing. Specifically, the state of the lights(green, yellow and red) is dependent on this timing. Also we will provide a reset signal input so that we can put the traffic light controller system to some known state.

With these we have the system port specifications. In VHDL language, this is the entity for the traffic light controller.

Next we need to analyze the traffic controller system.

We first need to settle down what happens at the initial state of the controller. Here when the system receives a reset signal, it should initialize the controller. We need to agree which lights should be green and which lights should be red initially. That is we need to agree on which is the major road and which is the minor road.

Let A be the major road and B the minor road. With this setting, the traffic lights on road A should be initially green and the lights on the road B should be initially red.

On Reset,

When the controller receives reset command the the lights on the A road should be green and lights on the B road should be red. That is, La should be green and Lb should be red. Note that there are two La and two Lb and they are always in the same state.

On car detection on road A,

Next we must consider what action should the controller take when there is detection of cars on the road A. The sensor on the road A are constantly monitoring the road. When there is a car on road A, the signal Sa remains high. But if there is no car the signal Sa goes low which causes the traffic light controller to change state. In this case, the light on road A changes from green to yellow for 3 sec. After 3 sec, the light then changes to red. At the instant when the light color on road A changes to red, the light color on road B changes to green.

On car detection on road B,

This is the same situation as that for road A. Consider the state when the light on road B is green, as long as there is traffic on the road B, the light remains green. But when there is no car on the road B, the light changes to yellow for 3 sec and then to red. When the light changes to red on road B, the light on road A changes to green.

So we can draw a state diagram for this traffic light controller. This is shown below.

There are four states S1, S2, S3 and S4. This diagram has already been explained above.

We need to assign the colors green, yellow and green to some binary codes. Let green be 00, yellow be 01 and red be 10 then we have the following diagram.

The VHDL code for this traffic light controller is below.

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity traffic_controller is 
	port (
		clk: in STD_LOGIC;
		rst: in STD_LOGIC;
		Sa: in STD_LOGIC;
		Sb: in STD_LOGIC;
		La: out STD_LOGIC_VECTOR (1 downto 0);
		Lb: out STD_LOGIC_VECTOR (1 downto 0));
end traffic_controller;

architecture traffic_controller_arch of traffic_controller is

type Traffic_controller_type is (
    S1, S4, S3, S2

signal Traffic_controller: Traffic_controller_type;


Traffic_controller_machine: process (clk)
	if clk'event and clk = '1' then
		if rst='1' then	
			Traffic_controller <= S1;


			case Traffic_controller is
				when S1 =>
					if Sa = '0' then	
						Traffic_controller <= S2;
					elsif Sa = '1' then	
						Traffic_controller <= S1;
					end if;
				when S4 =>
					Traffic_controller <= S1;
				when S3 =>
					if Sb='0' then	
						Traffic_controller <= S4;
					elsif Sb='1' then	
						Traffic_controller <= S3;
					end if;
				when S2 =>
					Traffic_controller <= S3;

				when others =>

			end case;
		end if;
	end if;
end process;

La <= "00" when (Traffic_controller = S1) else
      "10" when (Traffic_controller = S4) else
      "10" when (Traffic_controller = S3) else
      "01" when (Traffic_controller = S2) else

Lb <= "10" when (Traffic_controller = S1) else
      "01" when (Traffic_controller = S4) else
      "00" when (Traffic_controller = S3) else
      "10" when (Traffic_controller = S2) else

end traffic_controller_arch;

Digital Systems and Architecture / download ebook free

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The free ebook of the day is Digital Systems and Architecture. Download Digital Systems and Applications written by David Money Harris and Sarah Harris from the link below.

This book teaches the design of complete digital system starting from 1 and 0 notion of data, to combinational circuit, sequential circuit, FSM and design of MIPS(Microprocessor without Interlocked Pipeline Stages) microprocessor. Thus this book is helpful for learning how to design MIPS microprocessor.

There are many advantages of reading this book besides the basic of digital system. First, it teaches how to use VHDL and Verilog to digital system component. Second, it explains and illustrates real world architecture and microarchitecture of Intel IA-32 processors.

Download Link:

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