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Moore finite state machine VHDL code without enumerated state types

- Monday, July 6, 2015 No Comments
Most finite state machine vhdl are implemented using enumerated data type for the states of state machine. Here is an example of VHDL code of a finite state machine without using enumerated data types for the states. This code describes a moore machine with 3 states A, B and C.

library ieee;
use ieee.std_logic_1164.all;

entity moore_machine is
    port(
    x : in std_logic;
    rst, clk : in std_logic;
    z : out std_logic   
    );
end moore_machine;

architecture model of moore_machine is
signal state : std_logic_vector(1 downto 0);
constant A : std_logic_vector(1 downto 0) := "00";
constant B : std_logic_vector(1 downto 0) := "01";
constant C : std_logic_vector(1 downto 0) := "10";
begin
    Output_Logic : process(state)
    begin
        case state is
            when A => z <= '0';
            when B => z <= '0';
            when C => z <= '1';
            when others => z <= 'X';   
        end case;
    end process;
   
    Next_State : process(clk, rst)
    begin
        if (rst = '1') then
        state <= A;
       
        elsif rising_edge(clk) then
            case state is
                when A =>
                if(x = '1') then state <= B;
                else state <= A;
                end if;
               
                when B =>
                if(x = '1') then state <= C;
                else state <= B;
                end if;
                   
                when C =>
                if(x = '1') then state <= A;
                else state <= C;
                end if;
               
                when others => state <= "XX";
               
            end case;
        end if;
    end process;   
end model;

As can be seen in the above code, the current state of the FSM and the different states of the FSM are implemented inside the declaration section of the architecture. These are state, A, B and C. The current state called state is implemented as signal data type. The states A, B and C are implemented as constant data type.

state being 2 bits, can assume 00, 01, 10 and 11. Because we have arbitrarily chosen 3 states, the state when 00 is A, when 01 it is B and when it is 10 it is C. The state may assume 11 in which case, we have undefined output and undefined state.




VHDL code for ALU using Concurrent and Sequential Statements

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An ALU can be implemented in VHDL language using concurrent and sequential statements. Following VHDL code shows how ALU can be modelled using WHEN-ELSE and CASE statement in VHDL. WHEN-ELSE is concurrent statement and CASE statement is sequential. Both produces the same circuit in vhdl.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ALU is
    port(
    sel : in std_logic_vector(2 downto 0);
    X, Y : in std_logic_vector(3 downto 0);
    Z : out std_logic_vector(3 downto 0)
    );
end ALU;

architecture ALU_ARCH1 of ALU is
begin
    Z <= std_logic_vector(unsigned(X) + unsigned(Y)) when sel = "000" else
         std_logic_vector(unsigned(X) - unsigned(Y)) when sel = "001" else
         std_logic_vector(unsigned(X) * unsigned(Y)) when sel = "010" else
         std_logic_vector(unsigned(X) / unsigned(Y)) when sel = "011" else
         X and Y when sel = "100" else
         X or Y when sel = "101" else
         X xor Y when sel = "110" else
         not X when sel = "111";   
end ALU_ARCH1;

architecture ALU_ARCH2 of ALU is
begin
    process(sel, X, Y)
    begin
        case sel is
            when "000" => Z <= std_logic_vector(unsigned(X) + unsigned(Y));
            when "001" => Z <= std_logic_vector(unsigned(X) - unsigned(Y));
            when "010" => Z <= std_logic_vector(unsigned(X) * unsigned(Y));
            when "011" => Z <= std_logic_vector(unsigned(X) / unsigned(Y));
            when "100" => Z <= X and Y;
            when "101" => Z <= X or Y;
            when "110" => Z <= X xor Y;
            when others => Z <= not Y;
        end case;
    end process; 
end ALU_ARCH2


Make GUI in Visual Studio in 4 easy steps

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Making a GUI in Visual Studio is very easy. For a simple GUI like Hello World it requires only 4 easy steps. Other complicated project follow similar path.

1. Start Visual Studio


2. Create a New Project


3. Choose Windows Forms Application


3.  Component Placement and Coding

3.1 Drag and drop a button and text box components on to the form.

The button and text box are located in the Toobox.


To place click on the Button and then click on the Form1. Similarly place the text box.


Arrange the components are shown.


3.2 Coding

Double click on the Button and you will be brought to the button1_click method. Type the following inside the curely braces-

textBox1->Text="Hello World!";


4. Run the Program.

Run the Program by clicking on the Run and Build button on the toolbar.


Click on Yes in the message window that appears.

GUI program opens. Click on the button1.


Hello World! should appear in the text box.


VHDL example of using Shift_Right function

- Sunday, July 5, 2015 No Comments
Why Shift_Right function? In VHDL coding, shift_right function is very useful function because in hardware design it is often necessary to shift the bits inside a register. Shifting bits stored inside a register is often encountered.

An example of where this comes handy is while sending bits serially from a register.

Following figure illustrates the problem.


Here the Data is loaded into the register flip flop when for example sel is high. Otherwise the data is shifted from left to right and the bit stored in the LSB comes out first as Dout bit.

This type of register design with parallel load and serial out can be more easily implemented using shift_right function.

Following is the vhdl code that above design using shift_right function.


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity PISO is
    port(
    din : in std_logic_vector(3 downto 0);
    clk : in std_logic;
    sel : in std_logic;
    dout : out std_logic
    );
end SISO;

architecture PISO_arch of PISO is

begin
    process(clk)
    variable reg : unsigned(4 downto 0);
    begin
        if rising_edge(clk) then
            if sel = '1' then
                reg := unsigned(din) & '0';
            else
                reg := shift_right(reg,1);   
            end if;
        end if;
        dout <= reg(0);
    end process;
   
end PISO_arch;

To use the shift_register function following must be noted-
  • to use the numeric_std library
  • to declare the register as unsigned because shift_register functions on unsigned bits
  • to declare the register with one bit more than the input data