how to use exist statement in VHDL

Sunday, August 2, 2015
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Exit statement is used to exist a loop when a certain condition is satisfied. It is used as control mechanism to exist looping statements.
Following is an example of using exist statement in vhdl.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity VHDLdesign is
port(
D : in std_logic_vector(3 downto 0);
Q : out std_logic_vector(3 downto 0)
);
end VHDLdesign;
architecture design of VHDLdesign is
begin
process(D)
variable var : integer range 0 to 15 := 0;
begin
for k in 0 to 3 loop
if D(k) = '1' then
var := 1;
if var = 3 then
exit;
end if;
end if;
Q <= std_logic_vector(to_unsigned(var,4));
end loop;
end process;
end design;
In the above code, we have counted the number of 1 in a data stream of 4 bits. When there is a 1 then variable var is incremented by 1. But when the variable integer exceeds 3 then we exit the loop, that is counting 1's. The result of counting which could be 0,1 or 2 is outputted as Q.
We can use the label of a loop for exiting the loop. For example, in the above code, if we denote the loop as loop1 then we can rewrite the above code to exit the loop1 as follows
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity VHDLdesign is
port(
D : in std_logic_vector(3 downto 0);
Q : out std_logic_vector(3 downto 0)
);
end VHDLdesign;
architecture design of VHDLdesign is
begin
process(D)
variable var : integer range 0 to 15 := 0;
begin
Loop1: for k in 0 to 3 loop
if D(k) = '1' then
var := 1;
if var = 3 then
exit Loop1;
end if;
end if;
Q <= std_logic_vector(to_unsigned(var,4));
end loop;
end process;
end design;
Using loop label to exit loop becomes useful when there are multiple loops.
Following is an example of using exist statement in vhdl.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity VHDLdesign is
port(
D : in std_logic_vector(3 downto 0);
Q : out std_logic_vector(3 downto 0)
);
end VHDLdesign;
architecture design of VHDLdesign is
begin
process(D)
variable var : integer range 0 to 15 := 0;
begin
for k in 0 to 3 loop
if D(k) = '1' then
var := 1;
if var = 3 then
exit;
end if;
end if;
Q <= std_logic_vector(to_unsigned(var,4));
end loop;
end process;
end design;
In the above code, we have counted the number of 1 in a data stream of 4 bits. When there is a 1 then variable var is incremented by 1. But when the variable integer exceeds 3 then we exit the loop, that is counting 1's. The result of counting which could be 0,1 or 2 is outputted as Q.
We can use the label of a loop for exiting the loop. For example, in the above code, if we denote the loop as loop1 then we can rewrite the above code to exit the loop1 as follows
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity VHDLdesign is
port(
D : in std_logic_vector(3 downto 0);
Q : out std_logic_vector(3 downto 0)
);
end VHDLdesign;
architecture design of VHDLdesign is
begin
process(D)
variable var : integer range 0 to 15 := 0;
begin
Loop1: for k in 0 to 3 loop
if D(k) = '1' then
var := 1;
if var = 3 then
exit Loop1;
end if;
end if;
Q <= std_logic_vector(to_unsigned(var,4));
end loop;
end process;
end design;
Using loop label to exit loop becomes useful when there are multiple loops.