Here it is shown how NRZ encoded signal can be converted to Manchester encoded signal using verilog.

NRZ is a line coding techniques in which at each clock period, 0 is represented by 0V and 1 is represented by some high volt like 1V or 3.3V. In Manchester encoding 0 is represented by 0 in first half clock period followed by 1 in the other half clock period.

Often in digital communication system, NRZ signal are required to be converted to Manchester encoded signal.

The verilog code for converting of NRZ signal to Manchester signal in verilog is below. In the code x is the input NRZ signal and z is the output Manchester encoded signal.

module man_code(x,clk,rst,z);

input x;                    
input clk,rst;                  
output z;                

reg   state,next_state ;            
reg z;

parameter s0 =1'b0;              
parameter s1 = 1'b1;

always @(posedge clk or posedge rst)
 begin
if(rst)                    
state <= s0;
else                          
state <= next_state;
end

always @(state)                
begin
case(state)
s0:                          
begin
next_state <= s1;              
if(x)                
z<=1'b0;            
else
z<=1'b1;          
end
s1:                      
begin
next_state<=s0;            
if(x==0)          
z<=1'b0;        
else
z<=1'b1;        
end

default:              
next_state <= s0;    
endcase

end
endmodule

Testbench Code:

The testbench for the manchester encoder is provided below-

`timescale 1ns / 1ps
module man_code_tb;

defparam UUT.s0 = 1'b0;
parameter s0 = 1'b0;
defparam UUT.s1 = 1'b1;
parameter s1 = 1'b1;

reg x;
reg clk;
reg rst;
wire z;

man_code UUT (
.x(x),
.clk(clk),
.rst(rst),
.z(z));

  // set up clk
   always
   begin
      clk <= 0;
      #2.5;
      clk <= 1;
      #2.5;
   end

   initial
   begin
      // reset 
      rst <= 1;  
      #0.001;
 
 rst <= 0;  
      #0.001;
      //case 0
      x <= 0 ; 
      #10 ;
 
      x <= 0 ; 
      #10 ;
 
  x <= 1 ; 
      #10 ;
 
      x <= 0 ; 
      #10 ;
 
  x <= 1 ; 
      #10 ;
 
      x <= 1 ; 
      #10 ;
 
  x <= 0 ; 
      #10 ;
 
      x <= 1 ; 
      #10 ;
 
  x <= 1 ; 
      #10 ;
 
      x <= 0 ; 
      #10 ;
   
   end

endmodule

Stimulated Waveform:

Using the testbench we get the following stimulated digital waveform-

NRZ to manchester encoding verilog simulation waveform

In the above waveform, the clock period is 2.5ns. Each x NRZ signal bit is 10 ns. A short reset signal(rst) of 0.01ns(see above testbench code) was applied to initiate the simulation program. Had the rst signal been for example 2.5 ns we would get x and z signal shifted more towards the right in the above graph. As such, what it means is, we see exact correspondence of signals x and z in theory and books but in reality(at least in simulation) there is no exact timing correspondence between signal x and z as often seen  theoretically. By making rst signal as small as possible a better view of the conversion of signal x to z and mapping can be displayed.

For example, when we make rst signal period of 2.5 ns we get the below waveform. Compare the below waveform graph and the above one.

NRZ to manchester encoding verilog simulation waveform

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