How to use Xilinx Schematic editor with example of sequence detector | applied electronics engineering

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How to use Xilinx Schematic editor with example of sequence detector

By Applied Electronics - Wednesday, September 3, 2014 No Comments
This tutorial teaches how a Sequence Detector Circuit can be designed and verified using the Xilinx Schematic editor. The sequence to be detected is 101 and no reset, that is when sequence such as 10101... occurs the output will two times high, that is output z = 1 appears twice.

The first thing to do is to derive the sequential circuit for the sequence detector. This tutorial is about using Xilinx ISE schematic editor to draw the sequence detector circuit and hence assumes that you have done and derived the required circuit equation. 

To see the derivation of the sequence detector circuit design see earlier post - How to design Sequence Detector in 10 easy steps.

After you derived the the Flip Flop input equation and the equation for the output for the Sequence Detector you can implement the design in a schematic editor like the Xilinx ISE schematic editor.

The Flip Flop input equation and the equation for the output are as follows-

DA = A+ = BX'
DB = B+ = X
Z = XA

1. Create a new project in Xilinx.

2. At the toolbar, go to project and select New Source

3. Select Schematic and provide name to the new schematic page as shown below-

schematic page in xilinx

4. Draw the schematic as shown below 

creating schematic in xilinx

The Flip Flops and gates library can be found by clicking on the Add Symbol icon.

creating schematic in xilinx

5. Add a new vhdl file for testbench. 

Add new vhld testbench by going to Project > New Source and selecting VHDL Test Bench. Provide some suitable name and add the file.

Copy/ Paste the following just under the UUT section of the automatically generated test bench file.

clk_process : process
begin
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5 ns;
end process;
sti_process: process  
begin
x <= '0';
wait for 10 ns;
x <= '0';
wait for 10 ns;
x <= '1';
wait for 10 ns;
x <= '0';
wait for 10 ns;
x <= '1';
wait for 10 ns;
x <= '0';
wait for 10 ns;
x <= '1';
wait for 10 ns;-- 0010101110010110
x <= '1';
wait for 10 ns;
x <= '1';
wait for 10 ns;
x <= '0';
wait for 10 ns;
x <= '0';
wait for 10 ns;
x <= '1';
wait for 10 ns;
x <= '0';
wait for 10 ns;
x <= '1';
wait for 10 ns;
x <= '1';
wait for 10 ns;
x <= '0';
wait for 10 ns;
end process;

The complete testbench vhdl code is as below-


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
ENTITY seq_detect_seq_detect_sch_tb IS
END seq_detect_seq_detect_sch_tb;
ARCHITECTURE behavioral OF seq_detect_seq_detect_sch_tb IS

   COMPONENT seq_detect
   PORT( z : OUT STD_LOGIC;
          x : IN STD_LOGIC;
          clk : IN STD_LOGIC);
   END COMPONENT;

   SIGNAL z : STD_LOGIC;
   SIGNAL x : STD_LOGIC;
   SIGNAL clk : STD_LOGIC;

BEGIN

   UUT: seq_detect PORT MAP(
z => z,
x => x,
clk => clk
   );

clk_process : process
begin
clk <= '0';
wait for 5 ns;

clk <= '1';
wait for 5 ns;

end process;

sti_process: process
begin
x <= '0';
wait for 10 ns;

x <= '0';
wait for 10 ns;

x <= '1';
wait for 10 ns;

x <= '0';
wait for 10 ns;

x <= '1';
wait for 10 ns;

x <= '0';
wait for 10 ns;

x <= '1';
wait for 10 ns;-- 0010101110010110

x <= '1';
wait for 10 ns;

x <= '1';
wait for 10 ns;

x <= '0';
wait for 10 ns;

x <= '0';
wait for 10 ns;

x <= '1';
wait for 10 ns;

x <= '0';
wait for 10 ns;

x <= '1';
wait for 10 ns;

x <= '1';
wait for 10 ns;

x <= '0';
wait for 10 ns;

end process;

END;

6. Go to the Simulation tab and click on the Behavioral Check Syntax.

xilinx stimulation
7. Now click on the Stimulate Behavioral Model icon.

This generates the output waveform as shown below-

sequence detection waveform xilinx

The following shows the detection of 101 sequence:

sequence detection waveform xilinx

Another example of sequence detecting a sequence 010 is given in the blog post FPGA Programming Tutorial: 010 Sequence Detector with VHDL

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