Digital system is made up of smaller components and the way of putting these component together is by either structural and hierarchical coding. Below is an example of heirachical verilog coding using multiplexer as an example.

  The most basic elements or components in verilog are predefined primitives like AND, NOT, OR and other gates and transistors.

With these primitive we first create a 2-to-1 Multiplexer. The structure and verilog code for this as follows.

2-to-1 Multiplexer Structure

2-to-1 Multiplexer Verilog Code

4-to-1 Multiplexer

Using the above 2-to-1 multiplexer we can then build 4-to-1 Multiplexer. The structure of 4-to-1 Multiplexer and the verilog code is as follows.

4-to-1 Multiplexer Structure

As you can see two 2-to-1 Multiplexer have been used.

4-to-1 Multiplexer Verilog code

 We create 4-to-1 Multiplexer from two 2-to-1 Multiplexer instances called hi and lo.

You can further create higher level multiplexer by stacking more multiplexers. This method of building larger module from smaller by hierarchically inserting smaller module is called hierarchical modelling in verilog.

Hierarchical verilog coding is suitable and used for modelling or creating systems where identical components/modules is required. It speeds up the design process. Like the example above, for example, a full adder is designed using half adder and a larger adder is designed using full adders. Thus here too we can use hierarchical verilog coding. See How to design n -bit adder using hierarchical method in Verilog for this case.


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