An apparent solution to create an n-bit adder is to draw a hierarchical schematic that contains n full-adders. This procedure can be followed via utilizing Verilog, by first making a Verilog module for a full-adder after which defining a better-level module that makes use of n situations of the whole-adder. We will show how you can write the hierarchical code for a ripple-carry adder.

Suppose that we want to put into effect the whole-adder circuit given as shown in the figure below.


 The circuit has three inputs- Cin, x, and y , and produces the outputs s and Cout.  One way of specifying this circuit in Verilog is to use the gate-level primitives as shown below.

Code 1



Each and every of the three AND gates within the circuit is outlined by a separate declaration. Verilog allows for combining such statements into a single declaration as proven in below.

Code 2


 On this case, commas are used to separate the definition of every AND gate. Another way is to make use of realistic expressions as indicated below.

Code 3


 The XOR operation is denoted by way of the ∧ sign. Again, it is possible to mix the 2 continuous challenge statements right into a single assertion as proven below.

Code 4



Both of the above methods effect in the identical full-adder circuit being synthesized. We can now create a separate Verilog module for the ripple-carry adder, which instantiates the fulladd
module as a sub-circuit. One method of doing this is proven is shown below.

Code 5



 The module contains the code for a four-bit ripple-raise adder, named adder4.  One of the 4-bit numbers to be brought is represented with the aid of the four signals x3, x2, x1, x0, and the other number is represented with the aid of signals y3,y2,y1,y0. The sum is represented by means of three s- s2,s1 and s0. The circuit incorporates a carry input,carryin, into the least-signigicant-bit function and an output, carryout, from the most significant bit.

The above four-bit adder is described making use of 4 instantiation statements. Each and every instantiation starts with the name of the module, fulladd , that is being instantiated, followed by way of an instance name. The example names have got to be designated. The LSB within the adder is named stage0 and the MSB is stage3. The sign names in the adder4 module which can be to be linked to each and every input and output port on the fulladd module are then listed. These indicators are listed in the same order as within the fulladd module, namely the order Cin, x, y, s, Cout. In hierarchical design, the sign names associated with every illustration of the fulladd module implicitly specify how the entire-adders are connected collectively. For example, the elevate-out of the stage0 example is attached to the elevate-in of the stage1 illustration. The synthesized circuit has the identical structure as the one shown below.



The fulladd module could also be incorporated in the same Verilog source code file because the adder4 module, as done in code 5 above, but it may be also be incorporated in a separate file.  In the latter case, the location of the file fulladd needs to be indicated to the compiler.


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