The Story of Verilog | applied electronics engineering

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The Story of Verilog

By Applied Electronics - Tuesday, August 23, 2016 No Comments
For a very long time, programming languages akin to FORTRAN, Pascal, and C have been getting used to describe pc packages that have been sequential in nature. In a similar fashion, within the digital design discipline, designers felt the need for a average language to describe digital circuits. For this reason, Hardware Description Languages (HDLs) got here into existence. HDLs allowed the designers to mannequin the concurrency of processes determined in hardware factors. Hardware description languages corresponding to Verilog HDL and VHDL grew to be widespread. Verilog HDL originated in 1983 at Gateway Design Automation. Later, VHDL was developed below contract from DARPA. Each Verilog and VHDL simulators to simulate huge digital circuits
quickly gained acceptance from designers.

Despite the fact that HDLs were well known for good judgment verification, designers needed to manually translate the HDL-centered design right into a schematic circuit with interconnections between gates. The advent of common sense synthesis within the late Eighties changed the design methodology radically. Digital circuits might be described at a register transfer stage (RTL) via use of an HDL. For this reason, the fashion designer had to specify how the data flows between registers and how the design techniques the information. The small print of gates and their interconnections to put in force the circuit were mechanically extracted with the aid of good judgment synthesis tools from the RTL description.

Accordingly, logic synthesis pushed the HDLs into the forefront of digital design. Designers now not had to manually situation gates to construct digital circuits. They would describe intricate circuits at an summary stage in terms of functionality and data flow with the aid of designing those circuits in HDLs. Good judgment synthesis instruments would implement the specific functionality in phrases of gates and gate interconnections.

HDLs additionally started out for use for procedure-level design. HDLs have been used for simulation of process boards, interconnect buses, FPGAs (subject Programmable Gate Arrays), and pals (Programmable Array common sense). A common approach is to design each and every IC chip, using an HDL, after which affirm procedure performance by way of simulation.

Today, Verilog HDL is an accredited IEEE typical. In 1995, the normal typical IEEE 1364-1995 was approved. IEEE 1364-2001 is the trendy Verilog HDL standard that made colossal upgrades to the usual average. In mid 2004 the IEEE 1364 committee was disbanded, and maintenence on the typical used to be taken up by using the IEEE 1800 working team.


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