Vectored signals example in Verilog | applied electronics engineering


Vectored signals example in Verilog

By Applied Electronics - Wednesday, August 24, 2016 No Comments
Verilog HDL supports vectored signal which is a way to specify input, wires and output signal in groups instead of having to name each individual signal or wire. From the coding perspective this makes using verilog programming language convenient.

For the purpose of illustration we will show how to user vectored signal in verilog using the design of ripple carry adder which was illustrated How to design n -bit adder using hierarchical method in Verilog. The verilog code is re-shown below.

Ripple Carry Adder code:

 In the above code, each and every of the four-bit inputs and the four-bit output of the adder is represented utilizing single-bit signals. A more effortless process is to use multibit indicators, known as vectors, to symbolize the numbers. Simply as a number is represented in a common logic circuit as signals on multiple wires, it can be represented in Verilog code as a multibit vector. An example of an enter vector is

 This statement defines X to be a 4-bit vector.  Its individual bits can be mentioned by way of utilizing an index value in square brackets.  Thus, essentially the most-colossal bit (MSB) is referred to as X[3] and the least-huge bit (LSB) is X[0]. A two-bit vector that consists of the two center bits of X is denoted as [2:1]. The X symbol refers to the complete vector.

Making use of vectors we can specify the 4-bit adder shown in the following code.

 Ripple Carry Adder code using Vectored signal:

Furthermore to the input vectors X and Y, and output vector S, we choose to define the carry signals between the entire-adder levels as a 3-bit vector C[3:1].  Notice that the carry into stage0 is still known as carryin, even as the carry from stage3 is referred to as carryout.  The inner carry signals are outlined with the statement:

In the above verilog code, sign C[1] is used to attach the carry output of the entire-adder in stage 0 to the carry enter of the full-adder in stage 1. In a similar way, C[2] and C[3] are used to connect the opposite stages of the adder. The vector specification gives the bit width in rectangular brackets, as in X[3:0].  The bit width is particular utilizing the index of the MSB first and the LSB last. Consequently, X[3] is the MSB and X[0] is the LSB. A reverse ordering can be used. For illustration, Z[0:3] defines a four-bit vector where Z[0] is its MSB and Z[3] is its LSB.


No Comment to " Vectored signals example in Verilog "