FPGA devices are programmable hardware. Instead of writing C/C++ programs for your microcontrollers or processors, in FPGA world you can directly write the program into the hardware. But for programming FPGA device you need software or IDE to write HDL codes and burn them into the FPGA chip. Depending on which FPGA device you are using the software or FPGA IDE will be different. If you are using Xilinx FPGA devices then you will be using the Vivado IDE. The Xilinx FPGA software was previously known as Xilinx ISE design suite.

Here we show how to use Vivado FPGA software by walking through step by step process to create a new project. Then it will show you how to add VHDL source file and create D flip flop along with its testbench. In the next tutorial we will show how to run the simulation.

The first step is to start the Vivado design suite. When you do that, you should see the vivado start up window as shown below.


There you can see the various option you have. You can create a new project, open an existing project, open example projects, create and manage various task and there is also help section.

We want to create a simple project so we click on the Create New Project icon.


In the next screen you will be presented with options to specify the location of the project, name of the project, the targeted FPGA device and so on.

The first screen you will see is the following, where you can specify the name of the project and the location of the project. In this project we want to write simple VHDL code for a D flip flop and simulate it. There the name of the project is just dflipflop and the location is as shown. Here remember to check mark the field "Create project subdirectory" otherwise the project files will be created within the top specified directory folder. Since we want to create a new directory under the top directory folder we check mark this field. Then click Next.


Now in the next step you have the option to specify the type of the project. Select RTL project since we will be creating our own project.  Also remember to check mark the field "Do not specify sources at this time" otherwise you will be presented with another additional window in the next step that ask you to specify the file sources. After that click on Next.


Now that you have specified the name of the project, location for the project, type of the project you need to specify which part or board you are targeting. This means the FPGA device you are targeting. We do not use any FPGA device but only perform writing code and do simulation so we can use any of these. For this tutorial we have used the following(see figure). Then click on next.


Now we have completed the project wizard. You will be presented with summary of the project that you have just created. Click on Finish.


Once you click on Finish, Vivado software will initialize your project settings.


Once the project is set you will see the overall view of your new Project.  In the following picture, you can identify 3 pane- the project manager pane, the project summary pane and the design runs pane.



The project manager pane just list the folders and files in your project. The project summary gives you an overview of the state of the project, the parts used and other critical information. The Design Runs and other similar tabs at the bottoms gives you extra information about your project and state of the project. Errors, Logs,Reports and console are other tabs at the bottom.


The Flow Navigator pane is hidden by default. You can see this pane if you click on the double arrow icon.






If you click on this you will see the Flow Navigator.


The flow navigator is like the previous Xilinx ISE design suite flow navigator but has additional parts. The flow navigator shows you the states of different FPGA programming stages in Xilinx.

The next step is to add a VHDL file, write a D flip flop code with its testbench code. To do this we need to add new source file. We can add new source file in various ways. One of them is to click on the Add source button under the Project Manager which is under Flow Navigator.


As you can see from the above picture, when you click on the Add Sources you will see a screen Add Sources. There you need to select the Add or create design sources, then click Next.

After that you need to create the actual file by clicking on the add button.


Select VHDL as the file type, specify the name of the file as dff and click ok.


Then click on Finish to exit the file creation wizard.


Add this point, you will see another window pop up. This is for specifying the name of the architecture, specify ports and so on- all for the digital component which you are creating. Just click on OK because we can specify it later in the actual code.


After that you will see the new VHDL file named dff with behavioral architecture under the design sources folder and also the actual VHDL code for this file as shown below.


Then in the code editor window we write the VHDL code for D flip flop. Then save the file by using ctrl+s or by using the same button in the toolbar.


The code used for the D flip flop is as follows:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity dff is
  Port (
  x, clk : in std_logic;
  y : out std_logic
  );
end dff;

architecture Behavioral of dff is

begin
    process(x,clk)
    begin
        if rising_edge(clk) then
            y <= x;
         end if;
    end process;

end Behavioral;



The next step is to add a testbench for this D flip flop. To do this we add new vhdl source file like we did above. But in this case we will add the vhdl file to the simulation sourcesfolder. Right click on the simulation sources folder and then click on the Add Sources option.


Then select the Add or create simulation sources option and click on Next.


In the next screen specify the type and name of the file. The name of the file is dff_tb. Then click OK.


You will see a define module dialog box. Leave it in its default and click OK.


Now you will see a new file in the simulation sources folder. Double click it to bring it up in the editor window and write the following testbench code for the D flip flop created earlier.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity dff_tb is
end dff_tb;

architecture Behavioral of dff_tb is

    signal xt:     std_logic;
    signal clkt:    std_logic;
    signal yt:    std_logic;
   
    component dff
    port(
    x,clk:    in std_logic;
    y:    out std_logic
    );
    end component;

begin
   
    U_DFF: dff port map (xt, clkt, yt);

    -- concurrent process to offer clock signal   
    process
    begin
    clkt <= '0';
    wait for 5 ns;
    clkt <= '1';
    wait for 5 ns;
    end process;
   
    process
   
        variable err_cnt: integer := 0;
   
        begin
           
        -- case 1
        xt <= '1';
        wait for 12 ns;        
        assert (yt='1') report "Error1!" severity error;
        if (yt/='1') then
            err_cnt := err_cnt + 1;
        end if;
   
        -- case 2
        xt <=  '0';    
        wait for 28 ns;
        assert (yt='0') report "Error2!" severity error;
        if (yt/='0') then
            err_cnt := err_cnt + 1;
        end if;
   
        -- case 3
        xt <= '1';                     
        wait for 2 ns;
        assert (yt='0') report "Error3!" severity error;
        if (yt/='0') then
            err_cnt := err_cnt + 1;
        end if;
           
        -- case 4
        xt <= '0';
        wait for 10 ns;
        assert (yt='0') report "Error4!" severity error;
        if (yt/='0') then
            err_cnt := err_cnt + 1;
        end if;
   
        -- case 5
        xt <=  '1';       
        wait for 20 ns;       
        assert (yt='1') report "Error5!" severity error;    
        if (yt/='0') then
            err_cnt := err_cnt + 1;
        end if;
   
        -- summary of all the tests
        if (err_cnt=0) then            
            assert false
            report "Testbench of Adder completed successfully!"
            severity note;
        else
            assert true
            report "Something wrong, try again"
            severity error;
        end if;
   
        wait;
   
        end process;

end Behavioral;

Then save the file. You should see the following in the Sources windows.


So up to here we have created a new projet in Vivado, added two VHDL files- one D flip flop and the other its testbench. In the next Vivado tutorial we will simulate this design.


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