An instance or instances in Verilog language means copy of or use of. They are actual copy of primitives gates or transistor or could be instance of a larger design, for example, an adder(which is inturn build by primitives).

However, note that there is no instance keyword in Verilog(like module or port etc). It has only meaning attached to it when talking in verilog. You can think of verilog instance like instance of an object is C++ programming. When you create an instance in verilog you can give it a unique identification name.

Instance or instances in Verilog are used to build modules to larger digital system and to speed up programming.

Example

Consider a multiplexer as shown below.


 The mux is build using four primitive gates- two AND, one OR and one NOT gate. These four gates when used in mux code are referred to as instances. See the following corresponding verilog code.



Don't know what is FPGA? Then read FPGAs for Dummies.

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