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different ways to add instances to entity in VHDL

By Applied Electronics - Sunday, December 11, 2016 No Comments
This VHDL tutorial shows two method of adding instances to an entity. The two methods are via VHDL library reference and using configuration declaration block.

The entity was a odd parity generator whose schematic is shown below.
parity generator schematic
parity generator schematic
The various ways of adding the xor gate was briefly talked in that post.

2. Without component declaration

In this method, library feature is used to add the xor gate. By this what it means is that, the xor gate component are referred using library reference. And in this case there is no need to define the component within the architecture body.

the main code line that references the library is,

instance_unit_name : entity work.component_name(current_entity_architecture_name)

The instance_unit_name is the name of the instance which is newly created. The entity term is required, the work is the library(directory) where the component(eg xor_gate) resides and the current_entity_architecture_name is name of the current entity architecture name.

Let's see the code of that used component declaration is,

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity parity is
    Port ( x1 : in  STD_LOGIC;
           x2 : in  STD_LOGIC;
           x3 : in  STD_LOGIC;
           x4 : in  STD_LOGIC;
           y : out  STD_LOGIC);
end parity;

architecture parity_arch of parity is

component xor_gate
Port ( a1 : in  STD_LOGIC;
             a2 : in  STD_LOGIC;
             b : out  STD_LOGIC);
end component;

signal int1, int2: std_logic;

begin

xor_unit1 : xor_gate
port map(a1 => x1, a2 => x2, b => int1);
xor_unit2 : xor_gate
port map(a1 => x3, a2 => x4, b => int2);

y <= int1 xor int2;

end parity_arch;


The code in red is the component declaration. When using library reference to add component instances, the component declaration in red is not required. At the same time, the component instantiation lines in yellow needs to be changed such that it references to library where the component gate vhdl code resides.

Making the necessary changes, the code for the parity generator becomes-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity parity is
    Port ( x1 : in  STD_LOGIC;
           x2 : in  STD_LOGIC;
           x3 : in  STD_LOGIC;
           x4 : in  STD_LOGIC;
           y : out  STD_LOGIC);
end parity;

architecture parity_arch of parity is

signal int1, int2: std_logic;

begin

xor_unit1 : entity work.xor_gate(parity_arch)
port map(a1 => x1, a2 => x2, b => int1);
xor_unit2 : entity work.xor_gate(parity_arch)
port map(a1 => x3, a2 => x4, b => int2);

y <= int1 xor int2;

end parity_arch;


3. Using Configuration declaration:

Another method of adding component instance in the entity in VHDL is using configuration declaration. This differs from the above two methods in that, the port mapping is done in the architecture section while the VHDL library reference is done in a separate configuration section. Also the component declaration is added back.

The following code illustrates this.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity parity is
    Port ( x1 : in  STD_LOGIC;
           x2 : in  STD_LOGIC;
           x3 : in  STD_LOGIC;
           x4 : in  STD_LOGIC;
           y : out  STD_LOGIC);
end parity;

architecture parity_arch of parity is

component xor_gate
Port ( a1 : in  STD_LOGIC;
             a2 : in  STD_LOGIC;
             b : out  STD_LOGIC);
end component;

signal int1, int2: std_logic;

begin

xor_unit1: xor_gate port map(x1, x2, int1);
xor_unit2: xor_gate port map(x3, x4, int2);

y <= int1 xor int2;

end parity_arch;

configuration parity_config of parity is

for parity_arch 
for xor_unit1 : xor_gate
use entity work.xor_gate(xor_arch);
end for;
for xor_unit2 : xor_gate
use entity work.xor_gate(xor_arch);
end for;
end for;

end parity_config;


Thus there are different method of adding the component instance to a entity.

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