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How to design Full Adder in FPGA differently

By Applied Electronics - Tuesday, December 13, 2016 No Comments
You can implement adder or any FPGA MSI component in different ways if you know the logic. In this blogpost we show you how you can write and implement Full Adder with VHDL language. To that end we have to use FPGA software. Here we use Xilinx FPGA software now called Vivado.

The benefit of knowing this is FPGA beginners might wonder or might be confused about FPGA implementation of components. That is many might just get confused about the different ways FPGA design works. Futhermore, another advantage of learning this is that adders are the essential components in any FPGA implementation such as algorithm implementation, microprocessor design etc.

This FPGA Tutorial shows the different ways of writing and implementing Full Adder with VHDL. The first one is a direct approach and the second one is using component instantiation. The component instantiation method is based on reuseability of codes in FPGA or VHDL language. This method is more useful in terms of simplification of codes but the direct approach can also be useful in different situation, for example, quick illustration, prototyping and others.

The half adder circuit diagram is shown below,

half adder design

Using two such half adder and with an extra OR gate we can construct a Full Adder as shown,

full adder design


1. Using Direct Approach
2. Using Component instantiation

1. Using Direct Approach

We can use xor, and and or primitives function and operate them on the full adder input and outputs to build the full adder. The code is,

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity fulladder is
    Port ( in1 : in  STD_LOGIC;
           in2 : in  STD_LOGIC;
           c_in : in  STD_LOGIC;
           c_out : out  STD_LOGIC;
           sum : out  STD_LOGIC);
end fulladder;

architecture Behavioral of fulladder is

begin

sum <= c_in xor (in1 xor in2);
c_out <= (c_in and (in1 xor in2)) or (in1 and in2);

end Behavioral;

In the code above no component instances was used, and there was no need for internal signals.

2. Using Component Instantiation

In this method a smaller half adder component is build first and then used as component instances in the bigger full adder.

Half Adder VHDL code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity halfadder is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           s : out  STD_LOGIC;
 c : out STD_LOGIC);
end halfadder;

architecture halfadd_arch of halfadder is

begin
s <= a xor b;
c <= a and b;

end halfadd_arch;

This halfadder entity is used as component instance in the following Full Adder

Full Adder Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity fulladd is
    Port ( in1 : in  STD_LOGIC;
           in2 : in  STD_LOGIC;
           c_in : in  STD_LOGIC;
           c_out : out  STD_LOGIC;
           sum : out  STD_LOGIC);
end fulladd;

architecture fulladd_arch of fulladd is

signal sig1, sig2, sig3 : STD_LOGIC;

begin

halfadd_unit1: entity work.halfadder(halfadd_arch)
port map(
a => in1,
b => in2,
s => sig1,
c => sig2);
halfadd_unit2: entity work.halfadder(halfadd_arch)
port map(
a => sig1,
b => c_in,
s => sum,
c => sig3
);

c_out <= sig2 or sig3;

end fulladd_arch;

In this method, the half adder are called using library references by the line:
halfadd_unit1: entity work.halfadder(halfadd_arch)

Second, port mapping is performed eg,
port map(
a => in1,
b => in2,
s => sig1,
c => sig2);

Third, internal signals to the full adder are also defined,
signal sig1, sig2, sig3 : STD_LOGIC;


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