Here we show how to make a 4-bit full adder using 1-bit full adder in VHDL. The adder code was written and simulated using Aldec Active FPGA software. The result of adder design are shown to work in different data types- unsigned, 1's complement, 2's complement and in the sign magnitude representation.

There are different approach to design an adder. Here we take structural approach but you can also design adder using the "+" operator as was shown in the How to make Adder in VHDL? blog-post.

First let us show the 4 bit adder schematic that will be obtained after the adder is designed. The following shows the 4 bit Full Adder design schematic created in aldec FPGA software:

Full Adder design schematic created in aldec active hdl
Full Adder design schematic created in aldec active hdl



1-bit Full Adder VHDL code:

entity FA is
port(
a1, b1, c_in1 : in bit;
c_out1, sum1 : out bit
);
end FA;

architecture FA_arch of FA is
begin

c_out1 <= ((a1 xor b1) and c_in1) or (a1 and b1);
sum1 <= (a1 xor b1) xor c_in1;

end FA_arch;

4-bit Full Adder VHDL code:

entity adder is
port(
a, b : in bit_vector(3 downto 0);
c_in : in bit;
c_out : out bit;
sum : out bit_vector(3 downto 0)
);
end adder;

architecture adder_arch of adder is
signal int : bit_vector(3 downto 0);
begin

FA1 : entity work.FA port map(a1 => a(0), b1 => b(0), c_in1 => c_in, c_out1 => int(0), sum1 => sum(0));
FA2 : entity work.FA port map(a1 => a(1), b1 => b(1), c_in1 => int(0), c_out1 => int(1), sum1 => sum(1));
FA3 : entity work.FA port map(a1 => a(2), b1 => b(2), c_in1 => int(1), c_out1 => int(2), sum1 => sum(2));
FA4 : entity work.FA port map(a1 => a(3), b1 => b(3), c_in1 => int(2), c_out1 => int(3), sum1 => sum(3));

c_out <= int(3);

end adder_arch;

Testbench for 4-bit Full Adder:

entity adder_tb is
end adder_tb;

architecture TB_ARCHITECTURE of adder_tb is
-- Component declaration of the tested unit
component adder
port(
a : in BIT_VECTOR(3 downto 0);
b : in BIT_VECTOR(3 downto 0);
c_in : in BIT;
c_out : out BIT;
sum : out BIT_VECTOR(3 downto 0) );
end component;

-- Stimulus signals - signals mapped to the input and inout ports of tested entity
signal a : BIT_VECTOR(3 downto 0);
signal b : BIT_VECTOR(3 downto 0);
signal c_in : BIT;
-- Observed signals - signals mapped to the output ports of tested entity
signal c_out : BIT;
signal sum : BIT_VECTOR(3 downto 0);

-- Add your code here ...

begin

-- Unit Under Test port map
UUT : adder
port map (
a => a,
b => b,
c_in => c_in,
c_out => c_out,
sum => sum
);

-- Add your stimulus here ...
process begin

a <= "0011";
b <= "1011";
wait for 10 ns;

a <= "0111";
b <= "1010";
wait for 10 ns;

a <= "0010";
b <= "1000";
wait for 10 ns;

a <= "1001";
b <= "0011";
wait for 10 ns;

end process;

end TB_ARCHITECTURE;

configuration TESTBENCH_FOR_adder of adder_tb is
for TB_ARCHITECTURE
for UUT : adder
use entity work.adder(adder_arch);
end for;
end for;
end TESTBENCH_FOR_adder;

Simulation Waveforms:

1. Unsigned

full adder waveform in aldec active hdl

2. 2's Complement

full adder waveform in aldec active hdl

3. 1's Complement

full adder waveform in aldec active hdl

4. Signed Magnitude

full adder waveform in aldec active hdl


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