How to simulate verilog code in Xilinx? | applied electronics engineering

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How to simulate verilog code in Xilinx?

By Applied Electronics - Friday, December 9, 2016 No Comments
This tutorial shows you step by step how to simulate verilog code in xilinx FPGA software. Before doing that if you don't know what Verilog coding is we suggest you to read verilog books such as The Verilog Hardware Description Language or FPGA Programming by Verilog Examples so that you can follow this tutorial.

The step by step guide to using Xilinx FPGA software (or Vivado the new version of Xilinx but which is similar) for simulating Verilog codes are as follows.

Step 1: Open Xilinx ISE software



Step 2: Create a new project

Click on New then select New Project


You will see a window which lets you give the new project some name and save it in some folder. Provide some name for the Project, and save it to some folder-


When you click on Next you will see a window that allows you select the type of FPGA device that you want to work with, preferred HDL language and other project settings. Here select Verilog in the preferred language.


When you click on Next further, you will see a window that shows the summary of your Project.


Finally you have click on Finish and you should see the following window.


Step 3: Add new Verilog file to your Project

Now you have a new project. The next task is to add a Verilog source file. Select the FPGA device, right click on it and select New Source


When you click New Source a window as shown below will show up. In that window, select Verilog Module and provide some name for the file, In this tutorial we will be using the 4 to 1 mulltiplexer code from the previous blog post.



Click on Next and you will see a window just like the following picture in which you can specify the input or output or bidirectional port for you verilog module. In this example however we will copy and paste the Verilog code for the multiplexer designed in earlier post so we will not enter any ports names here and just click Next.


Then you will see a Summary information page.


When you click Finish you will see a new Verilog file with default Xilinx verilog template.


Step 4: Write your verilog code

Now copy the following verilog multiplexer code and paste it into the template.

module mux4x1(
    input a,b,c,d,
    input [0:1]sel,
    output reg f
    ); 
   
    always @*
        begin
    case(sel)
        2'b00: f = a;
        2'b01: f = b;
        2'b10: f = c;
        2'b11: f = d;
    endcase
    end
   
    endmodule

The following picture shows the template after you have copied and pasted into the default template.


Step 5: Check your Verilog Code Syntax

Click on Check Syntax under the Synthesize-XST as shown in the picture below.


If your verilog code syntax is correct then you will see a green check mark as shown in the figure above.

Step 6: Simulate with Isim simulator

To simulate the design with Xilinx ISim simulator first choose the Simulation view.


Then select your mux4x1 verilog file and click on the Behavioral Check Syntax icon under ISim Simulator.


If the syntax is correct then you will see a green check mark as shown above.

Now click on the Simulate Behavioral Model icon. Doing this opens the Isim Simulator as shown below.


Click on Restart button on the toolbar.


Right click on the signal a and select Force constant.


Then in the window that pops out, enter 0 in the Force to Value field to assign a a value of 0.


In the same way enter 0 for b, 1 for c and 1 for d.

Also in the same way set sel signal to 00 first. Then run the simulation for 10 ns.

Then next force the value for signal sel to 01 and run for 10 ns again.

Repeat this such that sel has the value 10 and 11 for 10 ns.

Ultimately we will have the following simulation trace for all combination of sel(00,01,10,11) as shown in the figure below.


The above simulation trace shows that the output f is correct according to the selections signal sel.

In this way we can simulate Verilog Code in Xilinx Verilog simulator.

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