how to use Modelsim for logic gate design and verification | applied electronics engineering

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how to use Modelsim for logic gate design and verification

By Applied Electronics - Saturday, December 10, 2016 No Comments
This is a quick video tutorial on how to use Modelsim for logic gate design and verification. An AND gate is constructed with verilog HDL and a testbench is also created to test it's logic. We start by creating a project in Modelsim, then create an AND gate and then the testbench. Finally operation of the gate is checked through simulation.

Watch the video below-



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