how to use the schematic editor of Active HDL FPGA software? | applied electronics engineering


how to use the schematic editor of Active HDL FPGA software?

By Applied Electronics - Monday, December 12, 2016 No Comments
Here we show how to use the schematic editor of Active HDL FPGA software. For this purpose we will design an adder subtractor circuit.

Let's say you have created a new workspace. Once you have created a new workspace to work with, you have number of option to proceed with your design. What this means is that you can start creating a design starting with block diagram, or start writing vhdl code for your design create state machine vhdl code and so on.

Let's start with a conceptual design where you can start with a block diagram. Right click on the Add New File > New and select Block Diagram.

Then a block wizard window appears which looks like the following,

start of block component wizard
 The first two wizard window ask you whether you want to add the file to the current design which you want so leave the checked box checked. Then the following 2nd window ask you what language you want to use which is VHDL so select VHDL. In the third step of the wizard you can specify the name of you block so name it something like add_subtract. You can optionally provide name for your entity and architecture body or leave it in default. Then finally you are allowed to specify the port names.

To create a new port click New button and enter it's name and the size of the port which is 8 bit(0 to 7 or 7 downto 0). Enter three inputs a, b which are 8 bits and sel which is 1 bit and one output port c which is 8 bit. The figure below shows how,

creating a block component
Now the definition of the block add_subtract is finished. Once you click on the Finish button then a sheet with previously defined ports appears.

schematic sheet of a block Now this block is the main entity of the design. Inside this or on this sheet we can create and place it's sub component blocks.

Let's illustrate this process of adding schematic component or sub-component with an example. First we will create adder subtractor VHDL code and convert that into schematic symbol and place that schematic symbol into the above main entity block.

To start with create a new VHDL file, and enter the following VHDL code,

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;

entity add_sub is
    port(a : in std_logic_vector(7 downto 0);
    b : in std_logic_vector(7 downto 0);
    c : out std_logic_vector(7 downto 0);
    sel : in std_logic
end add_sub;

architecture add_sub_arch of add_sub is

signal a1 : integer;
signal b1 : integer;
signal c1 : integer;

    a1 <= to_integer(signed(a));
    b1 <= to_integer(signed(b));   
    process (a1, b1)
        if sel = '1' then
            c1 <= a1 + b1;
            c1 <= a1 - b1;
        end if;
    end process;
    c <= std_logic_vector(to_unsigned(c1,7));

end add_sub_arch;

In the above VHDL code, what we have done is that a and b which are inputs are standard logic vectors(slv) but the + and - operator won't work on it. Therefore we have converted these slv to integer using the to_integer(signed(a)) and  to_integer(signed(a)) then we have done arthematic operation on these. Finally we have converted the output of the mathematical operation which is an integer c1 back to std_logic_vector using the line std_logic_vector(to_unsigned(c1,7)).

Notice that this conversion requires defining the VHDL library ieee.numeric_std.all.

The next step is to compile the code. Compile it and see whether there are any errors and if so fix it.

If the compile is sucessful then a schematic symbol for this vhdl entity will be created. Now we just have to add that to the top level entity which is the block created in the earlier.

Go back to the block sheet and click on the Symbol Toolbox available in the toolbar. Drag it into the sheet as illustrated by the figure below.

dragging component into a block sheet

You may rearrange the component and the ports.

placement of pins and components
 Now interconnect the ports.

interconnection of pins of VHDL components
 Save the design.

Now you then compile, create the vhdl code and stimulate whether this part works.

In addition to the above add_sub sub-module you may want to add more sub-component to the design.

In this way you can create a main component block and create and place different sub-component into the schematic sheet of the main component block.


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