How to write VHDL code for Ripple Carry Adder? | applied electronics engineering

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How to write VHDL code for Ripple Carry Adder?

By Applied Electronics - Wednesday, December 7, 2016 No Comments

This VHDL tutorial shows you how to write VHDL code for N-bit Ripple Carry Adder using for loop. This technique is requires less code than technique that uses one-bit full adder component instantiation.

A ripple carry adder is an digital adder that consist of N full adder cascaded in sequence. Each Full adder(FA)(see Full Adder VHDL design) has input bits a and b, previous carry input(cin) and produces sum(s) and carry output(cout).

The block diagram is shown below,

N bit full adder


It is possible create single full adder entity and then create a N bit adder by using component instantiation. This way of implementing the full adder will make the code large. Instead the following VHDL code shows how a N-bit full adder can be constructed using for loop for each bit of inputs and carry in to produce sum and carry out for each bit.

The following is VHDL code for 8-bit Ripple Carry Adder,

VHDL 8-bit Ripple Carry Adder Code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity carry_ripple_adder is
generic (N: integer:=8);
    Port ( a : in  STD_LOGIC_VECTOR(N-1 downto 0);
           b : in  STD_LOGIC_VECTOR(N-1 downto 0);
           cin : in  STD_LOGIC;
           s : out  STD_LOGIC_VECTOR(N-1 downto 0);
           cout : out  STD_LOGIC);
end carry_ripple_adder;

architecture Behavioral of carry_ripple_adder is

begin
process(a, b, cin)
variable carry: STD_LOGIC_VECTOR(N downto 0);
begin
carry(0) := cin;
for i in 0 to N-1 loop
s(i) <= a(i) xor b(i) xor carry(i);
carry(i+1) := (a(i) and b(i)) or (a(i) and carry(i)) or (b(i) and carry(i));
end loop;
cout <= carry(N);
end process;

end Behavioral;

Testbench for 8-bit Ripple Carry Adder
The following is the testbench for the above 8 bit ripple carry adder


  LIBRARY ieee;
  USE ieee.std_logic_1164.ALL;
  USE ieee.numeric_std.ALL;

  ENTITY testbench IS
  END testbench;

  ARCHITECTURE behavior OF testbench IS


          COMPONENT carry_ripple_adder
generic (N: integer:=8);
           Port (
a : in  STD_LOGIC_VECTOR(N-1 downto 0);
b : in  STD_LOGIC_VECTOR(N-1 downto 0);
cin : in  STD_LOGIC;
s : out  STD_LOGIC_VECTOR(N-1 downto 0);
cout : out  STD_LOGIC
);
          END COMPONENT;
       
signal test_input1, test_input2, test_s : std_logic_vector(7 downto 0):=(others => '0');
signal test_cin: std_logic:='0';
signal test_cout : std_logic:='0';

  BEGIN

          uut: carry_ripple_adder PORT MAP(
                  a => test_input1,
                  b => test_input2,
cin => test_cin,
s => test_s,
cout => test_cout
          );

     tb : PROCESS

     BEGIN

test_input1 <= "00110001";  --1
          test_input2 <= "00110010"; -- 2

        wait for 4 ns;

   test_input1 <= "00111001";  --9
          test_input2 <= "00111000"; -- 8

wait for 4 ns;
        wait;
     END PROCESS tb;

  END;

The digital waveform is shown below,

digital waveform for N bit full adder

See other FPGA tutorials.

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