Priority encoder is a encoder with priority. An encoder takes many
inputs and produces less output relative to the inputs. They find
application in for example in the routing of signal and in interupts
where when there are many interrupts a priority encoder can be used to
select that interupts with highest priority. If the number of input
lines is 2^n then the output lines is n for example 4x2 encoder.
In VHDL coding, conditional signal assignment statements using whenelse can be used to create a priority encoder.
The truth table we want to implement is,
The input is 4bit x and the output is y which is 3bit. If the nth bit of x is high encoder produces corresponding output y. For example when the 3rd bit of x is high x(3) then the output is 011.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity priority_encoder is
port(
x: in std_logic_vector(4 downto 1);
y: out std_logic_vector(2 downto 0)
);
end priority_encoder;
architecture priority_encoder_arch of priority_encoder is
begin
y <= "001" when(x(4)='1') else
"010" when(x(3)='1') else
"011" when(x(2)='1') else
"101" when(x(1)='1') else
"000";
end priority_encoder_arch;
Using Xilinx FPGA software we get the following schematic of the priority encoder code above.
In VHDL coding, conditional signal assignment statements using whenelse can be used to create a priority encoder.
The truth table we want to implement is,
Input(x)  Output(y) 

0000

000

1  

001

01 

010

001

011

0001

101

The input is 4bit x and the output is y which is 3bit. If the nth bit of x is high encoder produces corresponding output y. For example when the 3rd bit of x is high x(3) then the output is 011.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity priority_encoder is
port(
x: in std_logic_vector(4 downto 1);
y: out std_logic_vector(2 downto 0)
);
end priority_encoder;
architecture priority_encoder_arch of priority_encoder is
begin
y <= "001" when(x(4)='1') else
"010" when(x(3)='1') else
"011" when(x(2)='1') else
"101" when(x(1)='1') else
"000";
end priority_encoder_arch;
Using Xilinx FPGA software we get the following schematic of the priority encoder code above.
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