Design and simulation of 4 bit register in Active HDL FPGA software | applied electronics engineering

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Design and simulation of 4 bit register in Active HDL FPGA software

By Applied Electronics - Sunday, January 8, 2017 No Comments
Here we how Active-HDL FPGA software can be used to design and stimulate 4 bit register. The design process and simulation process are explained step by step with VHDL codes of the design and pictures.

Create a new workspace, name it and save it in some folder of your choice(create new folder). Then you should right click on the Add New File listed in the project workspace panel. Then you should select what new file you want to create, like VHDL file, verilog file or schematic file etc. In this case select VHDL file.

This brings up a window shown below which allows you to specify the name of the entity and architecture and create ports for the entity.

Type the name of your 4 bit register as shown. 

create a new vhdl source

Then create ports as shown.

create ports

Once you have done so you will have a vhdl file for your register. This vhdl file contains the entity, architecture name and the ports as was done in the during the register creation process done earlier.

What need to be done is to write the process or algorithm inside the architecture body that implements the 4 bit register.

First we want the output Dout to be all 4 zeros when the clear(CLR) is high. Then during each rising(or falling) edge of the clock(CLK) we want the data input Din to appear at the output pot Dout when the input Load is high.

This VHDL code for doing so is below:

architecture REG4 of REG4 is
begin

    process(CLK, CLR)
    begin
        if CLR = '1' then
            Dout <= (others => '0');
        elsif CLK'event and CLK = '1' then
            if Load = '1' then
                Dout <= Din;
            end if;
        end if;
       
    end process;     
 
end REG4;

Note that the name of the architecture and the entity is the same. This has no effect.

Now the whole VHDL code for the 4 bit register is below:

-------------------------------------------------------------------------------
--
-- Title       : REG4
-- Design      : microprocessor
-- Author      : radio
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity REG4 is
     port(
         CLK : in STD_LOGIC;
         CLR : in STD_LOGIC;
         Load : in STD_LOGIC;
         Din : in STD_LOGIC_VECTOR(3 downto 0);
         Dout : out STD_LOGIC_VECTOR(3 downto 0)
         );
end REG4;

architecture REG4 of REG4 is
begin

    process(CLK, CLR)
    begin
        if CLR = '1' then
            Dout <= (others => '0');
        elsif CLK'event and CLK = '1' then
            if Load = '1' then
                Dout <= Din;
            end if;
        end if;
       
    end process;     

end REG4;

Now we have to check for any error in the VHDL code. To do this, go to Design> Compile and see whether there is any error. The errors will be displayed in the console window. If any error click on the error line and Active-HDL simulator will highlight the line in the VHDL code where the error occured. Rectify the error accordingly.

Now we have to check the register using a testbench. The Active-HDL VHDL software has easy way of creating a testbench.

To create the testbench, right click on the icon EA which is the vhdl entity located inside the .vhd file in the workspace panel. This is shown below:

create testbech

This brings up the testbench wizard.

Select the design unit under test for which you want to create the testbench, in this case REG4.

testbench wizard

Specify test vector. In this case there is no test vector so click Next.

testbench wizard

Name the testbench entity, architecture etc, leave it in default and click Next.

testbench wizard

Click Next in this step also. We have option here to generate a file that contains timing information configuration which is not required here.

testbench wizard

After this the testbench VHDL code is generated and appears inside the folder called TestBench. See below figure.

generated testbench file

At this point, we have two option. We can write the testbench code for the input data inside the architecture body of the testbench code. Or we can directly go to the simulation process and then insert the input data(clk, clr also).

We will write the testbench input data inside the architecture body of the testbench code.

Go to the line where it is written- -- Add your stimulus here ...inside the architecture body of the testbench code.

Write down the following code beneath Add your stimulus here section

    -- Add your stimulus here ...
   
    Clock : process
    begin
        CLK <= '1';
        wait for 10 ns;
        CLK <= '0';
        wait for 10 ns;
    end process;
   
    Clear : process
    begin
        CLR <= '1';
        wait for 10 ns;
        CLR <= '0';
        wait for 10000 ns;
    end process;
   
    STIM: process
    begin
    Din <= "1001";
    LOAD<='0';
    wait for 350 ns;
    LOAD<='1';
    wait for 50 ns;
    LOAD<='0';
    wait for 100 ns;
    Din<="0110";
    wait for 200 ns;
    LOAD<='1';
    wait for 50 ns;
    LOAD<='0';
    wait for 150 ns;
    wait;
end process;

The entire testbench code is below:

library ieee;
use ieee.std_logic_1164.all;

    -- Add your library and packages declaration here ...

entity reg4_tb is
end reg4_tb;

architecture TB_ARCHITECTURE of reg4_tb is
    -- Component declaration of the tested unit
    component reg4
    port(
        CLK : in STD_LOGIC;
        CLR : in STD_LOGIC;
        Load : in STD_LOGIC;
        Din : in STD_LOGIC_VECTOR(3 downto 0);
        Dout : out STD_LOGIC_VECTOR(3 downto 0) );
    end component;

    -- Stimulus signals - signals mapped to the input and inout ports of tested entity
    signal CLK : STD_LOGIC;
    signal CLR : STD_LOGIC;
    signal Load : STD_LOGIC;
    signal Din : STD_LOGIC_VECTOR(3 downto 0);
    -- Observed signals - signals mapped to the output ports of tested entity
    signal Dout : STD_LOGIC_VECTOR(3 downto 0);

    -- Add your code here ...

begin

    -- Unit Under Test port map
    UUT : reg4
        port map (
            CLK => CLK,
            CLR => CLR,
            Load => Load,
            Din => Din,
            Dout => Dout
        );

    -- Add your stimulus here ...
   
    Clock : process
    begin
        CLK <= '1';
        wait for 10 ns;
        CLK <= '0';
        wait for 10 ns;
    end process;
   
    Clear : process
    begin
        CLR <= '1';
        wait for 10 ns;
        CLR <= '0';
        wait for 10000 ns;
    end process;
   
    STIM: process
    begin
    Din <= "1001";
    LOAD<='0';
    wait for 350 ns;
    LOAD<='1';
    wait for 50 ns;
    LOAD<='0';
    wait for 100 ns;
    Din<="0110";
    wait for 200 ns;
    LOAD<='1';
    wait for 50 ns;
    LOAD<='0';
    wait for 150 ns;
    wait;
end process;
   
end TB_ARCHITECTURE;

configuration TESTBENCH_FOR_reg4 of reg4_tb is
    for TB_ARCHITECTURE
        for UUT : reg4
            use entity work.reg4(reg4);
        end for;
    end for;
end TESTBENCH_FOR_reg4;

Once you have written the testbench code follow the steps below to stimulate the design.

Select the testbench EA file, right click it and click on Set as Top Level-

top level design

Go to Simulation and click on Initialize Simulation-

initialize simulation

Select and right click the reg4_tb(TB_ARCHITECTURE) listed in the left side of the design browser and click on Add to Waveform.
add to waveform

 This brings up the waveform viewer window as shown below. Now set the simulation time to 1000ns and click on Run Until button to start simulation.

simulated waveform

The below figure shows the waveform of the input data, clock, clear and load signal along with the output data.

simulated waveform

This completes the design and simulation of 4 bit register in Active HDL VHDL software.

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