VHDL language is rich, that is, it has number of language constructs which can be used to implement the same functions. Thus it makes possible to write multiplexer VHDL code in different ways. As an example we show how to write 2:1 multiplexer in VHDL language using when else statement and if then else statement.

1. Multiplexer using when-else statement

library ieee;
use ieee.std_logic_1164.all;

entity multiplexer is
    port(
    a, b : in std_logic;
    sel : in std_logic;
    f : out std_logic
    );
end multiplexer;

architecture model of multiplexer is
begin
     f <= a when sel = '1' else b;
end model1;

2. Multiplexer using with-select

library ieee;
use ieee.std_logic_1164.all;

entity multiplexer is
    port(
    a, b : in std_logic;
    sel : in std_logic;
    f : out std_logic
    );
end multiplexer;

architecture model of multiplexer is
begin
    with sel select f <=
    a when '1',
    b when others;
end model;

3. Multiplexer using if-then-else

 library ieee;
use ieee.std_logic_1164.all;

entity multiplexer is
    port(
    a, b : in std_logic;
    sel : in std_logic;
    f : out std_logic
    );
end multiplexer;

architecture model of multiplexer is
begin
    process(a,b,sel)
    begin
        if sel = '1' then
            f <= a;
        else
            f <= b;
        end if;
    end process;   
end model;

4. Multiplexer using case-when

 library ieee;
use ieee.std_logic_1164.all;

entity multiplexer is
    port(
    a, b : in std_logic;
    sel : in std_logic;
    f : out std_logic
    );
end multiplexer;

architecture model of multiplexer is
begin
    process(a,b,sel)
    begin
        case sel is
            when '1' => f <= a;
            when others => f <= b;
        end case;
    end process;
end model;


Simulation

The following shows simulated waveform in Active HDL FPGA software.


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