How to design ALU in Active HDL FPGA software | applied electronics engineering

How to design ALU in Active HDL FPGA software

By Applied Electronics - Tuesday, January 10, 2017 No Comments
We report design of Arithmetic Logic Unit(ALU) using Active HDL FPGA software. It is an important part of the CPU or processor. It performs logic operation such as or, and, nand etc and arithmetic functions such as addition, subtraction etc. These operations are performed depending upon the opcode code that is fed into it and produces output depending upon the opcode. Here we show how to design an ALU in VHDL and verify the output. The VHDL code is provided and the design can be simulated in any VHDL Software.

The design of ALU in VHDL is fairly simple. You have to decide what logic and arithmetic operation you wish to the ALU to perform. And you have to give each function an opcode which is some 4 bit code say.

Let x and y be 8 bit input, c be 1 bit carry in to the ALU and z be the output which is also 8 bits.

Then the VHDL code for the ALU is pretty straight forward. The code is below.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity alu is
port(x,y: in std_logic_vector(7 downto 0);
c : in std_logic;
opcode : in std_logic_vector(3 downto 0);
z : out std_logic_vector(7 downto 0)
);
end alu;

architecture arch of alu is

begin

with opcode select

-- logic unit
z <= x when "0000",
not x when "0001",
y when "0010",
not y when "0011",
x and y when "0100",
x nand y when "0101",
x or y when "0110",
x nor y when "0111",

-- arithmetic unit

x+1 when "1000",
y+1 when "1001",
x+y when "1010",
x-y when "1011",
0-x+y when "1100",
0-x-y when "1101",
x+y-1 when "1110",
x+y+c when others;

end arch;

In the above VHDL code, the when statements was used which is a concurrent statement. Notice that in the code, + and - operators were used in the arithmetic section. Because these operators were used the VHDL library std_logic_unsigned was used. If they were not used then the operator cannot act on the std_logic_vector inputs x and y.

The block diagram and the simulation results are now shown.

 How to design ALU in Active HDL FPGA software
Now the simulation results are shown for each of the opcodes.

Logic operation:

Arithmetic operation:

These simulator used was the active hdl vhdl software.