How to model amplitude modulator in VHDL | applied electronics engineering

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How to model amplitude modulator in VHDL

By Applied Electronics - Thursday, January 5, 2017 No Comments
This post shows ASK modulator design with VHDL code implemented in Xilinx and stimulated in modelsim. In earlier post a modem model design using system generator and vhdl language was illustrated. There the functionality of the modulator was ASK, PSK, FSK modulation. Here a single ASK modulation capable modulator design using VHDL is illustrated.

The ASK modulator implementation is based on ROM table from which sin wave required for ASK modulation are generated.

The following is the top level schematic diagram of ASK modulator generated by Xilinx that shows the inputs and output ports:



It has 3 inputs-  clk, rst and the data and two outputs the sin_out and y. The sin_out is the ASK signal. When data arrives they are mapped to value of sine amplitude using ROM table. The ROM table is itself implemented as a package that the sin_rom entity refers to.

The following are VHDL codes for ASK modulator, the Sine module and the ROM table as a package.

ASK Modulator:

The following code is ASK modulator implementation.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ASK is
        port ( data :  in   std_logic;
         rst:  in   std_logic;
clk  :  in   std_logic;
y    :  out  std_logic_vector(7 downto 0);
  sin_out:  out  std_logic_vector(7 downto 0));

end ASK;

architecture ASK_arch of ASK is
      component sin_rom  is
          port (
addr: in  std_logic_vector(5 downto 0);
              index: out std_logic_vector(7 downto 0)
 );
   end component;

signal sin : std_logic_vector(7 downto 0);
signal address : std_logic_vector(5 downto 0);

begin

  rom_map: sin_rom
               port map(  addr   =>  address,
                          index  =>   sin);

               sin_out <=  sin;

     process(clk)
 begin  
 if clk'event and clk = '1'then
      if rst   =  '1' then
     address <= "000000";
 else
     address <= address + 1;
                 end if;
            end if;

     end process;

    process(sin,data)

 begin

   if data = '1' then
     
  y <= sin ;

         else
   
 y  <=  conv_std_logic_vector(130,8);

   end if;

    end process;

end ASK_arch;

Sine Entity:

The sine ROM has one input addr and one output index. The input addr is an integer and the output is 8 bit vector.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.rom.all;

entity sin_rom is
       port ( addr: in  std_logic_vector(5 downto 0);
           index: out std_logic_vector(7 downto 0));
end sin_rom;

architecture Behavioral of sin_rom is

begin
index <= conv_std_logic_vector(rom(conv_integer(addr)),8);

end Behavioral;

ROM Table:

The ROM is a table implemented using array feature of VHDL.

library IEEE;
use IEEE.STD_LOGIC_1164.all;

package rom is
       constant rom_width: integer :=8;
       constant rom_length: integer :=64;
        subtype rom_word is  integer  range -255 to 255;
 type rom_table is array (0 to rom_length-1) of rom_word;
 constant rom : rom_table := ( 255,254,252, 249, 245, 239, 233, 225,
                                     217,207,197, 186, 174, 162, 150, 137,
                                     124,112 ,99, 87, 75, 64, 53, 43,
                                     34, 26, 19, 13, 8, 4, 1, 0,
                                     0, 1, 4, 8, 13, 19, 26, 34,
                                     43, 53, 64, 75, 87, 99, 112, 124,
                                     137,150,162, 174, 186, 197, 207, 217,
                                     225,233,239, 245, 249, 252, 254, 255
);
   end;

Simulation Result:


ASK waveform in modelsim

ASK waveform in modelsim

See more in FPGA tutorial page.

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