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How to run simulation in Active HDL FPGA software

By Applied Electronics - Saturday, January 7, 2017 No Comments
Aldec Active HDL is a nice FPGA IDE software for programming and simulation. In the post- Aldec Active HDL Simulator beginner Tutorial with VHDL, the step by step process involved in creating project, creating new vhdl file, compiling, setting up the simulation environment were illustrated. This post is about the 3 steps required to run the simulation properly- selecting top level design, simulation setting and initialization.

The design which has been used here consist of main design called mydesign. This mydesign is made of smaller components- and and xor gate. These(and and xor) gate are separately implemented as entity. The codes are provided are as follows-

mydesign.vhd


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mydesign is
Port ( a : in  STD_LOGIC;          
b : in  STD_LOGIC;
           
c : in  STD_LOGIC;
           
f : out  STD_LOGIC);

end mydesign;

architecture mydesign_arch of mydesign is
component and_gate
PORT(
and_in1 : in std_logic;
and_in2 : in std_logic;
and_out : out std_logic
);
end component;
component xor_gate
PORT(
xor_in1 : in std_logic;
xor_in2 : in std_logic;
xor_out : out std_logic
);
end component;
Signal s : std_logic;

begin

and_unit : and_gate port map(b, c, s);
    xor_unit : xor_gate port map(a, s, f);

end mydesign_arch;

configuration mydesign_config of mydesign is
    for mydesign_arch
        for and_unit : and_gate
        use entity work.and_gate(and_gate_arch);
    end for;
        for xor_unit : xor_gate
        use entity work.xor_gate(xor_gate_arch);
   end for;
   
   end for;
   

end mydesign_config;

and_gate.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity and_gate is
PORT(
and_in1 : in std_logic;
and_in2 : in std_logic;
and_out : out std_logic
);

end and_gate;

architecture and_gate_arch of and_gate is
begin 
and_out <= and_in1 and and_in2;

end and_gate_arch;

xor_gate.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity xor_gate is
PORT(
xor_in1 : in std_logic;
xor_in2 : in std_logic;
xor_out : out std_logic
);
end xor_gate;

architecture xor_gate_arch of xor_gate is
begin

xor_out <= xor_in1 xor xor_in2;

end xor_gate_arch;

mydesign_testbench.vhd

The testbench for this design is as follows-

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY mydesign_testbench IS
END mydesign_testbench;
ARCHITECTURE behavior OF mydesign_testbench IS 
    COMPONENT mydesign
    PORT(
         a : IN  std_logic;
         b : IN  std_logic;
         c : IN  std_logic;
         f : OUT  std_logic
        );
    END COMPONENT;
    
   signal a : std_logic := '0';
   signal b : std_logic := '0';
   signal c : std_logic := '0';
   signal f : std_logic;
BEGIN
   uut: mydesign PORT MAP (
          a => a,
          b => b,
          c => c,
          f => f
        );


   stim_proc: process
   begin
a <= '0';
b <= '0';
c <= '0';
      wait for 20 ns;
a <= '0';
b <= '0';
c <= '1';

      wait for 20 ns;
a <= '0';
b <= '1';
c <= '0';
      wait for 20 ns;
a <= '0';
b <= '1';
c <= '1';

      wait for 20 ns;
a <= '1';
b <= '0';
c <= '0';
      wait for 20 ns;
a <= '1';
b <= '0';
c <= '1';

      wait for 20 ns;
a <= '1';
b <= '1';
c <= '0';
      wait for 20 ns;
a <= '1';
b <= '1';
c <= '1';

      wait for 20 ns;

   end process;

END;

Adding files to the Aldec Active-HDL IDE

Once the above code is ready, a new workspace(project) is created using File > New > Workspace. Then a new design should be created. And finally the above 4 files should be added to the design. The files can be added in different ways. One can create a new vhdl source and copy paste the above code into the new blank vhdl source file for all 4 designs. Or, alternatively the files can be opened into the designed.

The following shows the project screenshot,

project window in active hdl
Add caption

Compilation

Design > Compile All would compile all the files.

Setting up Simulation in Active HDL:

The way to stimulate design in active-hdl simulator is a 3 step process. First is to set-up the testbench file as the top level design, then second, adjusting simulation setting and finally initialize the simulation before running the simulation.

Note that if one of the design is not set as the top level design, then one cannot initialize the simulation.

First, set the test bench, mydesign_testbench, as the top level design as shown below,

setting top level design in active hdl

Next, one can set various simulation options by going to Design > Settings. From there, one usually chooses the compilation and simulation tab for VHDL or verilog language as per the project. Here we can leave it in the default settings.

simulation setting in active hdl


Then finally initialize the simulation by selecting, Simulation > Initialize Simulation. Again note that the initialization will not work if the top level design is not selected.

initialization of simulation in aldec active hdl


Adding the waveform and Running the Simulation

Once the simulation is initialized, the next step is to add the signals to the waveform window. This is done by right clicking the top level design selected earlier and selecting Add to waveform as shown by the picture below,

adding waveform in active hdl


Now clicking on Run(F5) gives the waveform of the design as follows,

running simulation in aldec active hdl

aldec active hdl waveform

See other FPGA tutorials.

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