Active HDL is excellent FPGA software which has a feature of generating IP core. This feature facilitates one to create and develop codes. The IP core generator tool can be initiated during the design process which means that you do not have to generate the core at the start of your project.

The tool can be invoked from the Tool in the toolbar menu.

Active HDL IP core generator

Once you click that the following page will appear.

Active HDL IP core generator

On this page you can find overview of what the IP Core Generator is above and instructions on how to use the IP core generator.

On the left side of the page you can see number of different kinds of modules which are grouped according to their functions. There are groups such as basic elements which contains buffers, gates, constants, arithmetic function which includes multiplier, adder etc and other groups such as memory.

To illustrate how to use the IP core generator we can just click on the arithmetic group and select ALU.

Active HDL ALU IP core

This page allow one to define the entity/module name, the architecture name, the ports name and change signalling aspect of the module such as data bit width, clocking type- asynchronous or synchronous.

Once the desired name and data type fields are entered one just has to click the generate button on the lower right side of the page. This brings up the message-

IP core message

After this the IP core module is shown in the Design pane as shown,

IP core generator

Then you can adjust and add more functionality to the IP core.

So this VHDL/Verilog software has a nice feature which are useful for speeding up designs. It is similar to the Xilinx's IP core generator but the difference is that Active HDL is only a VHDL/Verilog sinulator whereas Xilinx is a complete design suite, meaning that FPGA devices can be programmed with it.

For example see How to add IP core in Xilinx


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