T flip flop are one kind of flip flop which is usually used for counter design. Below we show two VHDL codes or models for T flip flop.

Model 1:

library ieee;
use ieee.std_logic_1164.all;

entity tff is
    port(T : in std_logic;
    clk, rst : in std_logic;
    Q, Qn : out std_logic
    );
end tff;

architecture model1 of tff is
begin
    process(clk,rst,T)
    variable v : std_logic;
    begin
        if rst = '1' then
            v := '0';
        elsif rising_edge(clk) then
            if T = '1' then
                 v := not v;
            end if;
        end if;  
       
        Q <= v;
        Qn <= not v;      
       
    end process;
end model1;  

Model 2:

library ieee;
use ieee.std_logic_1164.all;

entity tff is
    port(T : in std_logic;
    clk, rst : in std_logic;
    Q, Qn : out std_logic
    );
end tff;


architecture model2 of tff is

begin
    process(clk,rst,T)
    variable v : std_logic;
    begin
    if rst = '1' then
        v := '0';
    elsif rising_edge(clk) then
        v := T xor v;
    end if;
  
    Q <= v;
    Qn <= not v;
  
end process;
end model2;

Simulation

The codes were compiled and simulated in Active HDL VHDL simulator.
 

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